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device power switch circuit package semiconductor technical data high voltage offline power switching regulator ordering information pin heatsink surface connected to pin 3 1. v cc 2. feedback input 3. ground 4. state control input 5. power switch pin order this document by mc33370/d tv suffix plastic package case 314e 5 1 12 mc33370t 0.9 6.8 mc33371t 1.5 4.8 mc33372t 2.0 3.8 mc33373t 2.7 3.0 mc33374t 3.3 straight lead on resistance ( ) peak current (a) 8 1 pin 1. v cc 2. feedback input 3. ground 4. state control input 5. power switch pin 6. ground 7. ground 8. ground p suffix plastic package case 626 12 mc33369p plastic dip8 0.5 12 mc33370p 0.9 6.8 MC33371P 1.5 4.8 mc33372p 2.0 4.0 mc33373ap 2.5 12 mc33369t 0.5 t suffix plastic package case 314d 1 5 12 mc33370tv 0.9 6.8 mc33371tv 1.5 4.8 mc33372tv 2.0 3.8 mc33373tv 2.7 3.0 mc33374tv 3.3 vertical mount 12 mc33369tv 0.5 1 motorola analog ic device data
the mc33369 through mc33374 are monolithic high voltage power switching regulators that combine the required converter functions with a unique programmable state controller, allowing a simple and economical powersystem solution for office automation, consumer, and industrial products. these devices are designed to operate directly from a rectified ac line source, and in flyback converter applications are capable of providing an output power in excess of 150 w with a fixed ac input of 100 v, 115 v, or 230 v, and in excess of 90 w with a variable ac input that ranges from 85 v to 265 v. this device series features a programmable state controller, an onchip 700 v sensefet ? power switch circuit, 700 v active offline startup circuit including a high voltage jfet and a low voltage mosfet, auto restart logic, fixed frequency duty cycle controlled oscillator, current limiting comparator with leading edge blanking, latching pulse width modulator for double pulse suppression, and a high gain amplifier with a bandgap reference. protective features include cyclebycycle current limiting, input undervoltage lockout with hysteresis, and a nonlatching thermal shutdown. these devices are available in economical 8pin dualinline and five pin to220 style packages. ? programmable state controller ? onchip 700 v sensefet power switch circuit ? rectified ac line source operation from 85 v to 265 v ? onchip 700 v active offline startup circuit ? latching pwm for double pulse suppression ? cyclebycycle current limiting ? input undervoltage lockout with hysteresis ? nonlatching internal thermal shutdown ? enhanced functionality over top200 and top221 series typical application this device contains 391 active transistors. programmable state controller pulse width modulator controller power switch circuit snubber feedback input v cc ground power switch pin + + + + dc output 2 1 5 state control input on/off 4 3 feedback ac input + startup circuit aux power supply ? motorola, inc. 1999 rev 3
mc33369 thru mc33374 2 motorola analog ic device data maximum ratings rating symbol value unit power switch and startup circuit (pin 5) voltage range pin 5 current peak during transformer saturation v 5 i 5(pk) 0.3 to 700 2.0 i lim max v a power supply voltage range (pin 1) v cc 0.3 to 10 v feedback input (pin 2) voltage range current v ir(fb) i fb 0.3 to 10 100 v ma state control input current (pin 4) i st 50 ma thermal characteristics p suffix, plastic package case 626 junctiontolead junctiontoair, 2.0 oz. printed circuit copper clad 0.36 sq. inch 1.0 sq. inch t and tv suffix, plastic package case 314 junctiontocase junctiontoair r q jc r q ja 5.0 45 35 2.0 65 c/w operating junction temperature t j 40 to +150 c storage temperature t stg 65 to +150 c electrical characteristics (pin 1 connected to pin 2, for typical values t j = 25 c, for min/max values t j is the operating junction temperature range that applies (note 2), unless otherwise noted.) characteristic symbol min typ max unit oscillator frequency (i fb = 4.0 ma) t j = 25 c t j = t low to t high f osc 90 70 100 110 115 khz amplifier and pwm comparator (pin 2) feedback input shunt regulation (i fb = 4.0 ma, t j = t low to t high ) voltage voltage temperature coefficient v reg(fb) v reg(fb) 8.3 8.6 0.005 8.9 v %/ c feedback input (i fb = 3.5 ma to 4.5 ma) resistance (t j = 25 c) resistance temperature coefficient (t j = t low to t high ) r i r i 14 19 0.3 23 %/ c feedback input current at threshold of duty cycle reduction mc33369, mc33370 mc33371 mc33372 mc33373a, mc33373 mc33374 i th(pwm) 1.2 1.3 1.4 1.5 1.6 1.6 1.8 2.0 2.1 2.2 2.1 2.3 2.4 3.0 3.2 ma amplifier/pwm gain (i fb = 3.5 ma to 4.5 ma) gain (t j = 25 c) gain temperature coefficient (t j = t low to t high ) a v a v 10 14 0.05 18 %/ma %/ c pwm duty cycle maximum (i fb = i cc1 ) minimum (i fb = 10 ma) d (max) d (min) 71 0.5 74 0.9 77 2.0 % shutdown latch external shutdown activation, current into pin 2 to set latch i sd 30 70 150 ma powerup reset threshold, pin 1 voltage to reset latch v rst 2.5 3.7 5.0 v state control (pin 4) input open circuit voltage (i fb = 4.0 ma) v oc(st) 3.2 3.55 3.8 v set comparator (v cc = v reg(fb) ) threshold voltage input clamp voltage (i in = 0.5 ma) input clamp current (v in = 8.6 v) v th(st) v clmp(st) i in(st) 4.1 5.0 4.4 5.5 1.0 4.7 6.5 v v ma toggle comparator (v cc = v reg(fb) ) threshold voltage (v in decreasing) hysteresis (v in increasing) input current (v in = 0.2 v) v th(tg) v h(tg) i in(tog) 1.6 1.8 200 40 2.0 v mv m a input reset current (v cc < v rst , v st = 1.1 v) i rst(st) 1.0 3.7 7.0 ma
mc33369 thru mc33374 3 motorola analog ic device data electrical characteristics (continued) (pin 1 connected to pin 2, for typical values t j = 25 c, for min/max values t j is the operating junction temperature range that applies (note 2), unless otherwise noted.) characteristic unit max typ min symbol power switch circuit (pin 5) on resistance pin 5 to pin 3 mc33369, mc33370 (i 5 = 50 ma) t j = 25 c t j = 125 c mc33371 (i 5 = 100 ma) t j = 25 c t j = 125 c mc33372 (i 5 = 150 ma) t j = 25 c t j = 125 c mc33373a (i 5 = 175 ma) t j = 25 c t j = 125 c mc33373 (i 5 = 200 ma) t j = 25 c t j = 125 c mc33374 (i 5 = 250 ma) t j = 25 c t j = 125 c r 5,3(on) 12 21 6.8 13 4.8 8.0 4.0 7.2 3.8 6.8 3.0 5.4 13.5 30 7.5 14.5 5.5 9.0 5.0 9.5 4.5 8.5 3.5 6.5 w breakdown voltage pin 5 (i 5(off) = 100 m a, t a = 25 c) v (br)5 700 v offstate leakage current pin 5 (v 5 = 700 v) t j = 25 c t j = 125 c i 5(off) 28 100 50 200 m a switching characteristics (v 5 = 50 v, r l set for i 5 = 0.7 i lim ) turnon time (90% to 10%) turnoff time (10% to 90%) t on t off 10 15 ns current limit and thermal protection current limit threshold (note 4, t j = 25 c) mc33369 mc33370 mc33371 mc33372 mc33373a mc33373 mc33374 i lim 0.44 0.8 1.3 1.8 2.2 2.4 2.9 0.5 0.9 1.5 2.0 2.5 2.7 3.3 0.56 1.0 1.7 2.2 2.8 3.0 3.7 a propagation delay, current limit threshold to power switch circuit output pin 5 (leading edge blanking plus current limit delay) t plh 280 ns thermal protection (note 1, 3) shutdown (junction temperature increasing) hysteresis (junction temperature decreasing) t sd t h 140 157 15 c
mc33369 thru mc33374 4 motorola analog ic device data electrical characteristics (continued) (pin 1 connected to pin 2, for typical values t j = 25 c, for min/max values t j is the operating junction temperature range that applies (note 2), unless otherwise noted.) characteristic unit max typ min symbol startup control (pin 1) undervoltage lockout startup threshold (v cc increasing) minimum operating voltage after turnon hysteresis v cc(on) v cc(min) v h 8.2 7.2 0.8 8.5 7.5 1.0 8.8 7.8 1.2 v startup circuit pin 1 output current (pin 5 = 50 v) v cc = 0 v v cc = 8.0 v i start 1.2 0.5 2.0 1.4 2.5 2.5 ma auto restart (c pin 1 = 47 m f, pin 5 = 50 v) duty cycle frequency d rst f rst 5.0 1.2 % hz total device (pin 1) power supply current after uvlo turnon power switch circuit enabled mc33369, mc33370 mc33371 mc33372 mc33373a, mc33373 mc33374 power switch circuit disabled i cc1 i cc2 0.5 0.65 0.8 0.95 1.1 0.6 1.2 1.4 1.5 1.7 1.8 1.0 1.7 1.8 1.9 2.1 2.2 1.2 ma notes: 1. maximum package power dissipation limits must be observed. 2. tested junction temperature range for the mc33370 series: t low = 40 ct high = +125 c 3.guaranteed by design only. 4.adjust di/dt to reach i lim in 5.0 m s.
mc33369 thru mc33374 5 motorola analog ic device data 50 11 0 50 4.6 50 120 v in , input voltage (v) t c , case temperature ( c) i in , state control input current (ma) v in , state control input voltage (v) v th , input threshold voltage (v) t c , case temperature ( c) figure 1. oscillator frequency change versus temperature t c , case temperature ( c) figure 2. state control input current versus input voltage figure 3. state control input threshold voltage versus temperature figure 4. state control input open circuit and clamp voltages versus temperature figure 5. power switch circuit output duty cycle versus feedback input current figure 6. feedback input current versus input voltage f 100 90 80 4.4 4.2 2.3 2.1 1.9 1.7 2.0 1.0 0 1.0 9.0 5.3 3.6 3.5 25 0 25 50 150 2.0 4.0 6.0 8.0 10 25 0 25 50 100 150 25 0 25 50 150 i fb = 4.0 ma 75 100 125 110 , normalized oscillator frequency (khz) osc 3.0 i fb = 4.0 ma t a = 25 c input zener clamp input open circuit voltage input pnp transistor clamp 75 125 i fb = 4.0 ma set comparator threshold, v in increasing toggle comparator hysteresis, v in increasing toggle comparator threshold, v in decreasing 75 100 125 5.7 i fb = 4.0 ma input zener clamp voltage at 10 ma input pnp clamp voltage at 0.5 ma input open circuit voltage 0 80 d, output duty cycle (%) i fb , feedback input current (ma) 60 40 20 0 2.0 4.0 6.0 10 8.0 auto restart hysteretic operation power supply current after uvlo turnon threshold of duty cycle reduction pin 1 connected to pin 2 t a = 25 c mc33374 mc33369/ mc33370 0 100 v fb , feedback input voltage (v) 60 40 20 0 2.0 4.0 6.0 12 8.0 i fb , feedback input current (ma) 10 80 pin 1 connected to pin 2 t a = 25 c input resistance v fb i fb
mc33369 thru mc33374 6 motorola analog ic device data 0 2.4 50 8.8 50 10 2.4 50 8.9 v cc , power supply voltage (v) v cc , startup and minimum operating voltage (v) t c , case temperature ( c) i lim , normalized current limit threshold t c , case temperature ( c) i start , startup circuit current (ma) v 5 , pin 5 voltage (v) v reg(fb) , shunt regulation voltage (v) figure 7. feedback input shunt regulation voltage and current versus temperature t c , case temperature ( c) figure 8. undervoltage lockout thresholds versus temperature figure 9. startup circuit current versus pin 5 voltage figure 10. startup circuit current versus power supply voltage figure 11. power switch circuit current limit threshold versus temperature 8.8 8.7 8.6 8.5 2.0 1.6 0.8 0 1.1 1.0 0.9 0.8 7.6 7.2 1.2 0.4 0.8 0 25 0 25 50 150 25 0 25 50 75 100 125 100 1000 2.0 4.0 10 25 0 25 50 0 2.0 i/ t, current rate of change (a/ s) figure 12. power switch circuit peak current versus current rate of change 2.0 4.0 6.0 10 1.4 1.0 1.2 75 100 125 shunt regulator voltage i fb = 4.0 ma feedback input current for 35% power switch circuit output duty cycle pin 1 connected to pin 2 2.0 3.0 4.0 5.0 6.0 i fb , feedback current (ma) 150 8.4 8.0 minimum operating voltage, v cc decreasing startup threshold voltage, v cc increasing 2.0 1.6 6.0 8.0 current into pin 5 current out of pin 1 v 5 = 400 v t case = 25 c 8.0 1.2 1.6 1.8 i pk , normalized peak current v 5(off) = 400 v t case = 25 c mc33369/ mc33370 mc33371 mc33372 mc33373a/ mc33373/ mc33374 75 100 125 150 v fb adjusted for an initial t on of 2.0 s 1.2 0.4 v cc = 5.0 v t case = 25 c current into pin 5 current out of pin 1 i start , startup circuit current (ma)
mc33369 thru mc33374 7 motorola analog ic device data 1.0 500 50 2.0 0 0 3.0 c oss , capacitance (pf) v 5 , pin 5 voltage (v) r 5,3(on) , normalized pin 5 to pin 3 onresistance t c , case temperature ( c) i 5(off) , offstate pin 5 current ( a) v 5 , pin 5 voltage (v) i 5 , pin 5 current (a) figure 13. power switch circuit current versus pin 5 voltage v 5 , pin 5 voltage (v) figure 14. normalized power switch circuit onresistance pin 5 to pin 3 versus temperature figure 15. power switch circuit offstate current versus voltage figure 16. power switch circuit capacitance versus pin 5 voltage 2.0 1.0 0 0.8 0.6 200 100 0 2.0 4.0 10 25 0 25 50 75 100 125 200 1000 10 1000 6.0 8.0 150 1.2 1.0 400 300 100 t on = 1.0 s t case = 25 c mc33369/ mc33370 mc33371 mc33372 mc33373 mc33374 1.4 1.8 1.6 t on = 1.0 s i 5 = 250 ma 400 600 800 10 1 10 2 10 3 10 4 mc33369/ mc33370 mc33371 mc33372 mc33373 mc33374 v cc power up sequence: 1) 0 to 8.6 v, startup circuit turn off 2) 8.6 v to 7.0 v, power switch circuit turn off 3) 7.0 v to 8.6 v, measure capacitance coss measured at 1.0 mhz with 50 mvpp t case = 25 c v cc power up sequence: 1) 0 to 8.6 v, startup circuit turn off 2) 8.6 v to 7.0 v, power switch circuit turn off 3) 7.0 v to 8.6 v, measure i 5 current power switch circuit breakdown voltage t case = 150 c t case = 50 c t case = 25 c startup circuit bias current mc33373a mc33373a figure 17. pin function description pin function description 1 v cc this is the positive supply voltage input. during startup, power is supplied to this input from pin 5. when v cc reaches the uvlo upper threshold, the startup circuit turns off and power is supplied from an auxiliary transformer winding. 2 feedback input this is the shunt regulator/amplifier input and is used to duty cycle control the power switch circuit. it has an 8.6 v threshold and normally connects to the converter output, or to a voltage that represents the converter output. 3 ground this pin is the control circuit and power switch circuit ground. it is part of the integrated circuit lead frame and is electrically common to the metal heatsink tab. 4 state control input this is a multifunction input that is designed to interface with a small number of external components to implement various methods of converter on/off control. 5 power switch pin this pin is designed to directly drive the converter transformer primary, and internally connects to the power switch circuit and startup circuit.
mc33369 thru mc33374 8 motorola analog ic device data figure 18. representative block diagram power switch circuit snubber feedback input v cc r pk power switch pin + + + + converter dc output 2 5 state control input on/off toggle 4 ac line input 1 thermal shutdown powerup reset external shutdown r s shutdown latch q internal bias state control ck q r divide by 8 s r q pwm latch minimum ontime delay leading edge blanking 8.5 v/ 7.5 v undervoltage lockout + 10 v driver shunt regulator/ amplifier 10 v 10 v oscillator duty cycle ramp clock + current limit comparator pwm comparator r fb 7.0 khz filter auto restart timing/ loop compensation/ power supply bypass 15 ground 3 startup circuit + 8.6 v i fb + auxiliary power supply feedback figure 19. pulse width modulation timing diagram normal pwm operating range output overload leading edge blanking input (power switch circuit current) power switch circuit gate drive pwm latch q output pwm comparator output oscillator clock oscillator duty cycle oscillator ramp feedback input (r fb voltage) current limit propagation delay current limit threshold minimum ontime
mc33369 thru mc33374 9 motorola analog ic device data operating description introduction the mc33369 thru mc33374 represent a new higher level of integration by providing on a single monolithic chip all of the active power, control, logic, and protection circuitry required to implement a high voltage flyback, forward, boost, or buck converter. this device series is designed for direct operation from a rectified 240 vac line source and requires minimal external components for a complete cost sensitive converter solution. potential markets include office automation, industrial, residential, personal computer, and consumer. a description of each of the functional blocks is given below, and the representative block diagram is shown in figure 18. oscillator the oscillator block consists of two comparators that alternately gate on and off a trimmed current source and current sink which are used to respectively charge and discharge an onchip timing capacitor between two voltage levels. this configuration generates a precise linear sawtooth ramp signal that is used to pulse width modulate the mosfet of the power switch circuit. during the charge of the timing capacitor, the oscillator duty cycle output holds one input of the driver low. this action keeps the mosfet of the power switch circuit off, thus limiting the maximum duty cycle. the oscillator frequency is internally programmed for 100 khz operation with a controlled charge to discharge current ratio that yields a maximum pwm duty cycle of 74%. the oscillator temperature characteristics are shown in figure 1. pwm comparator and latch the pulse width modulator (pwm) consists of a comparator with the oscillator ramp output applied to the inverting input, while the amplifier output is applied into the noninverting input. the oscillator clock output applies a set pulse to the pwm latch when the timing capacitor reaches its peak voltage, initiating power switch circuit conduction. as the timing capacitor discharges, the ramp voltage decreases to a level that is less than the amplifier output, causing the pwm comparator to reset the latch and terminate power switch circuit conduction for the duration of the rampdown period. this method of having the oscillator set and the pwm comparator reset the latch prevents the possibility of multiple output pulses during a given oscillator clock cycle. this circuit configuration is commonly referred to as double pulse suppression logic. a timing diagram is shown in figure 19 that illustrates the behavior of the pulse width modulator. shunt regulator/amplifier feedback input, pin 2, connects to the internal shunt regulator/amplifier. this input is used as a means to close the feedback loop for converter output regulation. the internal circuitry consists of an amplifier with a precise threshold that drives a mosfet in a manner that forms an active shunt regulator. the initial current that flows into pin 1 is used to bias the internal circuitry. any additional current is in excess flows into pin 2, and is shunted through resistor r fb to ground. the voltage developed across r fb is used to adjust the pwm comparator threshold, which in turn controls the pwm duty cycle. the duty cycle is inversely proportional to the input current level that in excess of about 2 ma, and is reduced at a rate of about 14% per ma, refer to figure 5. a 7.0 khz low pass filter is placed between r fb and the pwm input. this filter attenuates any switching noise that may be present and reduces the possibility of output pulse width jitter. the amplifier gain is set by the dynamic impedance of the feedback input and is nominally centered at 18 . the dynamic impedance of this pin combined with the external resistive and capacitive components determines the control loop characteristics of the converter. the feedback input has a temperature compensated threshold of 8.6 v and is used as a voltage reference in nonisolated output applications. the input dynamic resistance is shown in figure 6. external shutdown and latch a latching shutdown feature has been incorporated into this device series to eliminate the possibility of converter runaway output voltage during a sudden load removal. the external shutdown block sets the shutdown latch when the feedback input current exceeds 60 ma. when set, the latch holds the mosfet of the power switch circuit off, and the startup circuit hystereticly regulates the v cc pin 1 voltage between 8.5 v to 7.5 v. in order to resume the switching operation, the shutdown latch must be reset by the powerup reset block. this can be accomplished directly by momentarily pulling the v cc pin 1 below the 3.7 v powerup reset threshold, or indirectly by removing, waiting, and then restoring power to the converter input. the powerup reset block automatically resets the shutdown latch each time power is applied to the device. current limit comparator and power switch circuit this device series uses cyclebycycle current limiting as a means of protecting the output switch circuit from overstress. each oncycle is treated as a separate situation. current limiting is implemented by monitoring the output switch circuit current buildup during conduction, and upon sensing an overcurrent condition, immediately turning off the switch circuit for the duration of the oscillator rampdown period. the power switch circuit is constructed as a sensefet circuit with a high voltage jfet in series with a low voltage mosfet. the drain of the high voltage jfet is connected to pin 5. the gate of the jfet is grounded. the source of the jfet is connected to the drain of the low voltage mosfet. the mosfet has two sources of different size with a known ratio of about 1:100. one source of the mosfet is connected to pin 3 and provides the main current conduction path between pin 5 and pin 3. the second source of the mosfet is used for current sensing by conducting a small percentage of the current between pin 5 and pin 3 through a ground referenced sense resistor, r pk . the voltage across sense resistor r pk represents the current from pin 5 to pin 3 divided by the known ratio of the mosfet sources. the sensefet circuit allows a virtually lossless method of monitoring the current from pin 5 to pin 3. the current limit comparator detects if the voltage across r pk exceeds the reference level that is present at the noninverting input. if exceeded, the comparator quickly resets the pwm latch, thus protecting the power switch circuit. figure 11 shows that this detection method yields a relatively constant current limit threshold over temperature. the high voltage power switch circuit is integrated with the control logic circuitry and is designed to directly drive the converter transformer. the power switch circuit is capable of switching 700 v with an associated current from pin 5 to pin 3 that ranges from 0.9 a to 3.3 a. proper voltage snubbing on pin 5 during converter startup and overload is mandatory for reliable device operation. a leading edge blanking circuit was placed in the current sensing signal path to prevent a premature reset of the pwm latch. a potential premature reset signal is generated each time
mc33369 thru mc33374 10 motorola analog ic device data the power switch circuit is driven into conduction and appears as a narrow voltage spike across the current sense resistor r pk . the spike is due to the low voltage mosfet gate to source capacitance, transformer interwinding capacitance, and output rectifier recovery time. the leading edge blanking circuit has a dynamic behavior that masks the current signal until the power switch circuit turnon transition is completed. the current limit propagation delay time is typically 280 ns. this time is measured from when an overcurrent appears in the power switch circuit, to the beginning of turnoff. care must be taken during transformer saturation so that the maximum device current limit rating is not exceeded. figure 20. startup and normal operation timing diagram 8.5 v 7.5 v 0 v 0 v flyback voltage rectified line voltage switching shunt regulation threshold feedback input voltage (pin 2) power switch voltage (pin 5, pin 3) switching disabled normal operation startup figure 21. auto restart operation timing diagram 8.5 v 7.5 v 0 v 0 v flyback voltage rectified line voltage switching feedback input voltage (pin 2) power switch voltage (pin 5) switching disabled auto restart operation with overloaded or shorted output startup startup circuit duty cycle during auto restart, external shutdown, thermal shutdown, and state control off mode 35% 65% switching switching disabled switching switching disabled startup circuit hysteretic regulation on i start off i cc1 on i start off i cc2 on i start off i cc2 on i start off i cc1 eight cycles 1278 1 7 28 1 5% power switch circuit duty cycle during auto restart 95%
mc33369 thru mc33374 11 motorola analog ic device data startup circuit contained within the mc33369 thru mc33374 is a startup circuit that is governed by the state control block. the startup circuit includes a high voltage jfet and a low voltage mosfet. the drain of the high voltage jfet is connected to pin 5. the gate of the jfet is grounded. the source of the high voltage jfet is connected to the drain of the low voltage mosfet. the jfet pinches off and clamps the voltage on the drain of the mosfet to a low voltage between 1824 volts. a resistance of 550k ohms is connected between the drain and gate of the low voltage mosfet. the low voltage on the drain and gate of the mosfet simplifies construction of the startup circuit. this circuitry yields an increase in converter efficiency by the elimination of an external startup resistor and its associated power dissipation that is common in most of the offline converters that utilize a uc3842 type of controller. rectified ac line voltage is applied to the startup circuit from pin 5. this enables the startup circuit to provide charge current to the v cc bypass capacitor that connects from pin 1 to ground. when v cc reaches the uvlo upper threshold of 8.5 v, the startup circuit is turned off to complete the startup phase. the ic then commences normal operation. as the converter output approaches regulation, the auxiliary transformer winding begins to provide operating bias. all of the required device power is now efficiently converted down directly from the rectified ac line. the startup circuit will provide an initial charging current of 2.0 ma when powered from 400 v. this current will decrease as the v cc pin voltage rises or if the device is powered from a lower input voltage, refer to figures 9 and 10. the startup circuit is rated at a maximum of 700 v with the v cc pin shorted to ground. undervoltage lockout an undervoltage lockout comparator is included to guarantee that the integrated circuit has sufficient voltage to be fully functional before the output stage is enabled. the uvlo comparator monitors the feedback input voltage at pin 2 and when it exceeds the startup threshold of 8.5 v, the startup circuit turns off, the internal bias block is switched on, and the power switch circuit is enabled. to prevent erratic switching as the threshold is crossed, 1.0 v of hysteresis is provided. this level of hysteresis ensures that there is sufficient energy stored in the v cc bypass capacitor to power the bias circuitry until auxiliary power supply takes over. if the converter output is nominally loaded, regulation will be established and the optoisolator will provide sufficient current into the feedback input to keep the v cc bypass capacitor charged. figure 20 shows the timing waveforms during startup and normal operation. if the converter output is overloaded or shorted, the device will enter into the auto restart mode. this happens when the optoisolator is not able to provide sufficient current into the feedback input to keep the v cc bypass capacitor charged. when the capacitor voltage falls below the minimum operating threshold of 7.5 v, the uvlo comparator switches the internal bias block off, and disables the power switch circuit. the startup circuit is turned on and the v cc bypass capacitor begins charging. when the uvlo startup threshold is reached, the startup circuit again turns off, the internal bias block is switched on, and the divide by 8 counter is clocked. since the power switch circuit is now disabled by the divide by 8 counter, the optoisolator will not provide current to the v cc bypass capacitor, the capacitor will discharge. the uvlo comparator and startup circuit will regulate the capacitor voltage in a hysteretic mode, varying between 7.5 v to 8.5 v, with an effective rampup duty cycle of approximately 35%. the divide by 8 counter will enable the power switch circuit to burst at the 100 khz oscillator frequency on every eighth rampdown cycle. the device will remain in the auto restart mode until the output overload or short is removed and the threshold of regulation can again be reached. the purpose of the divide by 8 counter is to reduce the power switch circuit and output rectifier power dissipation when the converter is subjected to an output overload or short. the counter effectively limits the average switching duty cycle to approximately 5%. figure 21 shows the timing waveforms when in auto restart mode. thermal shutdown and package the internal thermal shutdown block protects the device in the event that the maximum junction temperature is exceeded. when activated, typically at 157 c, one input of the driver is held low to disable the power switch circuit. when disabled, the uvlo comparator and startup circuit regulate the v cc pin voltage in the hysteretic mode. thermal shutdown activation is nonlatching and the power switch circuit is allowed to resume operation when the junction temperature falls below 140 c. the thermal shutdown feature is provided to prevent catastrophic device failures from accidental overheating. it is not intended to be used as a substitute for proper heatsinking. the die in the 8pin dualinline package is mounted on a special heat tab copper alloy lead frame. the tab consists of pins 3, 6, 7, 8 is specifically designed to improve the thermal conduction from the die to the printed circuit board. this permits the use of standard layout and mounting practices while having the ability to halve the junction to air thermal resistance. the die in the 5 pin to220 style package is mounted directly on a copper alloy heat tab. this metal tab is exposed on the back side of the package for heatsink attachment and is electrically common to the device ground, pin 3. a wide variety of to220 style heatsinks are commercially available for enhancing the thermal performance and converter output power capability. state control the state control block is designed to interface with a small number of external components to implement various methods of converter on/off control. by utilizing the distinctive features of the state control input, this device series can be programmed to enter into either the standby* or operating mode in response to an appropriate input stimulus. this stimulus can come from a user interface pushbutton switch, an optically coupled microcontroller output signal, a combination of both, or other circuit configurations. the state control logic can be disabled and made to appear transparent when converter on/off control is not required. figures 22 and 23 respectively show the state control operating table, and the control block along with seven input examples. the state control block consists of a resistor bias network, toggle and set comparators for threshold detection, an input clamp to provide drive for an opto light emitting diode, control logic elements for storing the operating state, and a reset mosfet for discharging an
mc33369 thru mc33374 12 motorola analog ic device data external capacitor. the state control input is internally biased at 3.55 v when the v cc input is regulated at 8.6 v. this internal bias can be overridden and driven either low or high by an external signal in order to trip one of the comparators. the toggle and set comparator thresholds are respectively at 1.8 v and 4.4 v. the comparator outputs are processed and stored by the state control logic block which in turn controls the startup circuit, internal bias block, and the divide by 8 reset. circuit a shows an input configuration for manual toggle operation. a toggle request is made each time the pushbutton switch is pressed and released. when the toggle comparator detects a request, its output clocks the state control logic, resulting in a converter mode change. successive toggle requests causes the converter to alternate between the standby* and operating modes. when in standby* mode, the uvlo comparator and startup circuit regulate the v cc pin voltage in the hysteretic mode, and there is not any voltage present at the converter output. circuit b configures the input to interface with a microcontroller for graceful shutdown operation. graceful shutdown is an advanced form of power management where the microcontroller has the overriding responsibility for determining if and when the converter enters into the standby* mode. this is usually programmed to occur after the microcontroller completes a set of housekeeping routines. a toggle request is made each time the pushbutton switch is pressed and released. when the set comparator detects a request, its output sets the state control logic, causing the converter to enter the operating mode. if the converter was initially operating, no mode change takes place. note that each toggle request is conveyed to the microcontroller via opto a. a current path for biasing the light emitting diode is provided by the series resistor and the internal 5.5 v input clamp. the microcontroller receives and processes the toggle request and upon completion of a maintenance routine, it sends a toggle confirm signal back to the state control input via opto b. this signal is detected by the toggle comparator and the converter enters into the standby* mode. with this circuit configuration, the user only has control of the standby* to operating mode transition. the user can request the operating to standby* mode transition, but the microcontroller has total control on executing the request. circuit c configures the input for brownout protection. the cathode of the zener diode connects to the rectified and filtered ac line voltage that appears at the positive terminal of bulk capacitor c1. with appropriate zener diode and resistor values, the state control input voltage can be set to fall below 1.8 v during a brownout condition. this results in a toggle request that causes the converter to incisively change from operating to standby* mode without any converter output voltage bounce. when the ac line voltage returns back to nominal, the voltage at the state control input rises, causing the set comparator to change the converter mode from standby* to operating. note that when the converter is in standby*, the set comparator threshold will be lower than specified, and is approximately 3.84 v. this is because v cc is regulated in the hysteretic mode between 7.5 v to 8.5 v. circuit d shows a method of accomplishing digital on/off control of the converter. pullup resistor r serves to bias the set comparator for turnon, while the npn transistor biases the toggle comparator for turnoff. an economical optocoupler can be used if galvanic isolation of the signal source is required. capacitor c st shown in each of the examples provides an important programming function. a small value capacitor ( 0.05 m f) serves to filter noise that may be coupled into the state control pin, thereby preventing false triggering of the comparators. a relatively large value capacitor ( 2.0 m f) will delay the initial rise of the state control voltage during startup. this action results in the converter powering up in standby* rather than the operating mode. circuit e configures the state control input to provide a powerup time delay of the converter. upon the initial application of ac power, the large value of capacitor c st causes the toggle comparator to place the converter in standby*. when pullup resistor r charges c st to the set comparator threshold, the converter changes to the operating mode. a graph of powerup time delay versus resistance for three values of c st is shown. the circuits shown in the example in circuit f on page 13 exemplifies two possible methods of disabling the state control block on/off capability, thus rendering it transparent. this feature is useful in applications where converter on/off control is not desired. when nominal ac line voltage is applied to the converter input, the resistor circuit will cause the set comparator to place the converter in the operating mode. the resistor value is not critical, but it should be at least 5.0 k to insure proper device startup. the converter will also assume the operating mode if the state control input is left open or unconnected. due to the relatively high input impedance, this input may be susceptible to noise pickup. a small bypass capacitor in the range of 1.0 nf to 50 nf is recommended for c st . the converter will assume the operation mode with either of these circuits. applications the to220 devices have a single ground, pin 3, that serves as both a sense point for the shunt regulator/amplifier and the high current return path for the power switch circuit. do not attempt to construct a converter circuit on a wirewrap or plugin prototype board . in order to ensure proper device operation and stability, it is important to minimize the lead length and the associated inductance of the ground pin. this pin must connect as directly as possible to the printed circuit ground plane and should not be bent or offset by the board layout. the power switch pin 5 can be offset using a tv suffix product if additional layout creepage distance is required. due to the potentially high rate of change in switch circuit current, components r3 and c5 must be connected to ic1 through separate and short copper traces. this will significantly reduce the level of switching noise that can be imposed upon the feedback control signal. figures 24 through 27 show a universal input 52 watt 90 watt converter with the associated test data. the converters were constructed and tested using the printed circuit board layout shown in figure 28. the board consists of a fiber glass epoxy material (fr4) with a single side of two ounce per square foot copper foil. it is designed as a general purpose single output laboratory test vehicle and therefore does not contain an input electromagnetic interference (emi) filter. the board layout is capable of encompassing the wide range of output power available from the to220tv package devices by providing a means to accept several component
mc33369 thru mc33374 13 motorola analog ic device data sizes and styles. note that there are multiple positions for output filter capacitors c8 and c11, allowing up to four capacitors in parallel. the various positions for transformer t1 will accomodate four core/bobbin sizes, consisting of e19/8/5 (e187), e22, e25/10/6 (e250), and e28. unused pins must be removed from the bobbin. a choice of four to220 style heatsinks can be used for integrated circuit ic1 and output rectfier d7. they are available from several manufacturers including aavid engineering. the table shown below lists the aavid part numbers along with the associated thermal characteristics. the extruded heatsink must be drilled and tapped to allow attachment of the device and the printed circuit board. aidp heatsink aavid part number style thermal resistance ( c/w) 592502b03400 stamped 24 at 2.0 w 593002b03400 stamped 14 at 4.0 w 593202b03500 stamped 10.4 at 5.0 w 590302b03600 stamped 9.2 at 5.0 w 604953b02500 extruded 6.0 at 15 w the maximum output power that can be obtained from a given converter design is limited by the maximum operating junction temperature and current limit threshold of the device selected. the table below provides a general guide for device selection assuming the following conditions: discontinuous mode flyback operation wide range input operation from 92 vac to 276 vac bulk capacitor c1 ripple voltage 25 vpp at 92 vac input converter efficiency of 75% ambient temperature of 25 c adequate heatsinking for a junction temperature 150 c device converter output power (w) mc33369p 12 mc33370p 20 MC33371P 30 mc33372p 35 mc33373ap 40 mc33369t/tv 12 mc33370t/tv 25 mc33371t/tv 45 mc33372t/tv 60 mc33373t/tv 75 mc33374t/tv 90
mc33369 thru mc33374 14 motorola analog ic device data figure 22. state control operating table (circuits a through d of figure 23) initial state subsequent state ac line voltage converter mode input (pin 4) converter mode description voltage mode capacitor stimuli mode toggle operation (circuit a) nominal standby don't care pulsed low 1.8 v operating the converter changes from standby to operating mode by the toggle comparator. nominal operating don't care pulsed low 1.8 v standby the converter changes from operating to standby* mode by the toggle comparator. microcontroller graceful shutdown (circuit b) nominal standby don't care pulsed high 4.4 v operating converter mode toggle requested. the set comparator changes the converter mode from standby to operating. nominal operating don't care pulsed high 4.4 v operating converter mode toggle requested. no mode change takes place since the converter was initially operating. the change request is communicated to the mcu via opto a. nominal operating don't care pulsed low 1.8 v standby converter mode toggle is confirmed by the mcu via opto b. the converter mode changes from operating to standby. brownout protection (circuit c) nominal to brownout operating don't care biased low 1.8 v standby the ac line voltage level changes from nominal to brownout and zener diode breakdown ceases. the lower divider resistor biases the toggle comparator input low, changing the converter mode from operating to standby. brownout to nominal standby cst 0.05 m f biased high 3.85 v operating the ac line voltage level changes from brownout to nominal and zener diode commences breakdown. this biases the set comparator input high, changing the converter mode from standby to operating. digital on/off control (circuit d) nominal standby don't care biased high 4.4 v operating the transistor is off and the collector resistor biases the set comparator input high, placing the converter in the operating mode. nominal operating don't care biased low 1.8 v standby the transistor is on and the collector biases the toggle comparator input low, placing the converter in the standby mode. delayed powerup (circuit e) zero to nominal off cst 2.0 m f pulsed low by cst 1.8 v set high 4.4 v off delay operating discharged capacitor cst causes the toggle comparator to change the control logic state. the converter is placed in the standby mode with the power switch circuit disabled. when cst charges above 4.4 v, the set comparator changes the converter mode from standby to operating. powerup (circuits a, and b) zero to nominal off cst 0.05 m f none operating application of ac line power causes converter operation. the state control input is presently configured to be transparent and the control logic has no effect during powerup. zero to nominal off cst 2.0 m f pulsed low by cst 1.8 v standby discharged capacitor cst causes the toggle comparator to change the control logic state. the converter is placed in the standby mode with the power switch circuit disabled. note: when the converter is in the standby mode, there is not any voltage present at the output.
mc33369 thru mc33374 15 motorola analog ic device data figure 23. state control block with input control examples state control logic from v cc voltage detector outputs startup circuit to internal bias and divide by 8 reset 10 v state control input set comparator toggle comparator 1.8 v/ 2.0 v 8.6 v 3.55 v 4.4 v 1.8 v reset 116 k input clamp 5.5 v v cc 1 4 power switch pin 5 10 v 165 k primary common c st toggle request 10 to 10 k r primary common 5.0 k to 100 k r c st v cc 1.0 nf to 50 nf primary common 100 k to 300 k r c st v cc 10 f to 100 f primary common 5.0 k to 100 k r c st v aux 1 = converter off 0 = converter on primary common c st v bulk v z r2 r1 primary common r c st v aux toggle request microcontroller printer port secondary common control outputs + isolation boundary toggle confirm powerup time delay versus resistance r, resistance (k ) 100 200 150 8.0 4.0 0 12 100 f 10 f c st = 50 f t , time delay (s) dly digital on/off control of the converter is accomplished with a small signal npn transistor. an optocoupler can be used if galvanic isolation is required. digital on/off control (circuit d) powerup time delay (circuit e) a programmed powerup time delay can be implemented with the addition of a simple rc circuit. state control disabled (circuit f) the state control block on/off capability can be disabled and made to appear transparent by either connecting a pullup resistor from the input to v cc or a small value capacitor from the input to primary common. this input should not be left unconnected since it has a relatively high impedance and may be susceptible to noise pickup. brownout protection (circuit c) choose vac (on to off) and vac (off to on) thresholds. determine converter output power p o , efficiency , and input bulk capacitance c blk . mcu graceful shutdown (circuit b) manual toggle operation (circuit a) resistor r is required for proper toggle functionality when operating the device at an elevated temperature with long leads to the pushbutton switch. r 2 r 1 v blk(max) v z 3.84 or v blk(min) v z 1.8 v z 1.88 v blk(min) 0.88 v blk(max) v blk(max) vac (off to on) 2 1.4 v blk(min) vac (ontooff) 2 p o vac (ontooff) 2f ac c blk 1.4 internal state control block functional diagram mc33369 thru mc33374
mc33369 thru mc33374 16 motorola analog ic device data figure 24. universal input 52 w offline converter + + 15 v/3.5 a dc output pb1 on/off toggle 92 to 276 vac input d4 d2 d3 d1 1n5406 f1 3.0 a + + r3 3.6 c5 50 c4 0.01 r7 100 1/2 ic2 moc8103 mc 33374 ic1 z1 1.5ke200a d5 mur160 c13 1.0 c12 150 c8 470 c11 470 ++ c2 50 pf r2 3.9 k c14 1.0 nf ic3 tl431b r6 75 k r4 270 d7 mbr20100ct r5 15 k c1 100 t1 c7 0.1 1/2 ic2 moc 8103 l1 5.0 h + c6 10 d6 mur 120 figure 25. converter test data test conditions results line regulation v in = 92 vac to 276 vac, i o = 3.5 a = 2.0 mv load regulation v in = 115 vac, i o = 0.35 a to 3.5 a = 9.0 mv v in = 230 vac, i o = 0.35 a to 3.5 a = 13 mv output ripple v in = 92 vac to 276 vac, i o = 3.5 a total = 170 mv pp efficiency v in = 115 vac, i o = 3.5 a 84.4% v in = 230 vac, i o = 3.5 a 86.2% ac input power v in = 115 vac, converter toggle off 0.06 w v in = 230 vac, converter toggle off 0.19 w c8, c11 = c12 = ic1, d7 = l1 = t1 = sanyo oscon #16sa470m, 470 m f/16v. sanyo oscon #10sa150m, 150 m f/16v. mc33374, mbr20100 mounted on aavid #590302b03600 heatsink. coilcraft s5088a, 5.0 m h, 0.011 . coilcraft w7422a primary: 49 turns of # 24 awg, pin 6 = start, pin 5 = finish. two layers 0.002o mylar tape. secondary: 9 turns of # 21 awg, 2 strands bifilar wound, pins 1 and 2 = start, pins 9 and 10 = finish. auxiliary: 7 turns of #24 awg wound in center of bobbin, pin 7 = start, pin 4 = finish. two layers 0.002o mylar tape. gap: 0.017o total for a primary inductance (l p ) of 345 m h, with a primary to secondary leakage inductance of 14 m h. core: ferrite international e24/25 (e25/10/6) tsf7070 material. bobbin: philips e2425pcb110, pins 3 and 8 removed. this data was taken with the components listed below mounted on the printed circuit board shown if figure 28.
mc33369 thru mc33374 17 motorola analog ic device data figure 26. universal input 90 w offline converter + + 15 v/6.0 a dc output pb1 on/off toggle 92 to 276 vac input d4 d2 d3 d1 1n5406 f1 5.0 a + + r3 3.6 c5 50 c4 0.01 r7 100 1/2 ic2 moc8103 mc 33374 ic1 z1 1.5ke200a d5 mur160 c13 1.0 c12 150 c8 1000 c11 1000 ++ c2 50 pf r2 3.9 k c14 1.0 nf ic3 tl431b r6 75 k r4 270 d7 mbr20100ct r5 15 k c1 330 t1 c7 0.1 1/2 ic2 moc 8103 l1 3.3 h + c6 10 d6 mur 120 figure 27. converter test data test conditions results line regulation v in = 92 vac to 276 vac, i o = 6.0 a = 24 mv load regulation v in = 115 vac, i o = 0.6 a to 6.0 a = 26 mv v in = 230 vac, i o = 0.6 a to 6.0 a = 10 mv output ripple v in = 92 vac to 276 vac, i o = 6.0 a total = 105 mv pp efficiency v in = 115 vac, i o = 6.0 a 83.2% v in = 230 vac, i o = 6.0 a 85.4% ac input power v in = 115 vac, converter toggle off 0.07 w v in = 230 vac, converter toggle off 0.17 w c8, c11 = c12 = ic1 = z1 = d7 = l1 = t1 = sanyo oscon #16sa1000m, 1000 m f/16v. sanyo oscon #10sa150m, 100 m f/16v. mc33374 mounted on aavid #604953b02500 extruded heatsink. the heatsink must be drilled and tapped to allow device & pcb attachment. 1.5ke200a with cathode lead soldered in the center of a 5/8o x 3/4o x 0.025o thick ushaped copper heatsink. mbr20100 mounted on aavid #590302b03600 heatsink. coilcraft pcv033210, 3.3 m h, 0.005 . coilcraft w7518a primary: 34 turns of # 24 awg, pin 9 = start, pin 6 = finish. two layers 0.002o mylar tape. secondary: 5 turns of # 20 awg, 2 strands bifilar wound, pins 4 and 5 = start, pins 1 and 2 = finish. two layers 0.002o mylar tape. auxiliary: 4 turns of #24 awg wound in center of bobbin, pin 10 = start, pin 7 = finish. two layers 0.002o mylar tape. gap: 0.022o total for a primary inductance (l p ) of 290 m h, with a primary to secondary leakage inductance of 7.2 m h. core: tdk pc40 ei28z, pc40 material. bobbin: tdk be281110cpl, pins 3 and 8 removed. this data was taken with the components listed below mounted on the printed circuit board shown if figure 28.
mc33369 thru mc33374 18 motorola analog ic device data figure 28. printed circuit board and component layout (circuit of figures of 23 and 25) c1 ??? ??? ??? ??? ??? ??? ??? ??? ??? ??? (top view) r1 z1 c2 c3 c14 d1 + d3 d4 f1 d5 r7 r2 ic1 c4 c5 ac line input + + 1 r3 c6 + ic2 d6 e 22 e 28 1 1 r4 r5 r6 ic3 c7 + + + + c11 c10 + c12 c13 l1 c9 c8 + t1 e19/8/5 e25/10/6 1 1 dc output toggle on/off pb1 caution! high voltages d2 d7 mc33369 thru 74 4.00 (bottom view) 2.50
mc33369 thru mc33374 19 motorola analog ic device data figure 29. snubber and damper circuits + + + mur160 ic1 c3 r1 d5 + rc damper rcd snubber r2 c2 converter figure component values snubber output power t1 primary leakage inductance 24 20 k 2.0 w 14 m h 50 w 26 7.2 m h 90 w damper 10 k 3.0 w 0.1 m f 400 v 6.2 k 1.0 w 47 pf 500 v 0.1 m f 400 v 6.2 k 1.0 w 47 pf 500 v r1 c3 r2 r2 pin 5 turnoff voltage 6.0 8.0 2.0 4.0 10 0 t, turnoff time ( s) 400 300 200 100 0 , pin 5 voltage (v) v 5 pin 5 turnoff voltage 6.0 8.0 2.0 4.0 10 0 t, turnoff time ( s) 400 300 200 100 0 sufficient snubbing insufficient snubbing substrate forward biased , pin 5 voltage (v) v 5 figures 24 and 26 use zener diode z1 to limit the voltage on pin 5 and a damper circuit consisting of resistor r2 and capacitor c2. the zener can be replaced with the snubber circuit shown above consisting of resistor r1 and capacitor c3. the component values selected must insure that the turnoff voltage on pin 5 never exceeds 700 v under all line voltage and load current conditions when using a transformer with the highest anticipated leakage inductance. there must also be sufficient snubbing and damping to prevent the turnoff voltage on pin 5 from ringing below ground. this will cause forward biasing of the substrate and can result in additional device power dissipation and converter instability. suggested snubber and damper component values for figures 24 and 26 are listed in the table above. the snubber and damper circuits will greatly reduce the radiated switching noise but there will be a slight penalty in converter efficiency. figure 30. recommended printed circuit board layout pb1 r3 c5 c4 r7 ic1 high switch current return from ground pin to negative terminal of capacitor c1. high switch current from transformer t1 to power switch pin. feedback and v cc bias return to auxiliary winding ground terminal of transformer t1. feedback and v cc bias source. in order to ensure proper device operation, the integrated circuit ground, pin 3, must connect as directly as possible to the printed circuit board ground foil. the ground pin should not be bent or offset by the board layout. the power switch circuit, pin 5, can be offset if additional creepage distance is required using a tv suffix product. components r3 and c5 connect through seperate and short copper traces to ic1. this will reduce the level of undesirable switching noise that appears on the feedback input and v cc pins.
mc33369 thru mc33374 20 motorola analog ic device data figure 31. transformer auxiliary winding elimination zener shunt regulator method + + + ic1 in965b 10 k 4 w figure 32. transformer auxiliary winding elimination bipolar transistor series regulator method + + + ic1 in965b 82 k 0.5 w 5.1 k 0.5 w mje 13003
mc33369 thru mc33374 21 motorola analog ic device data figure 33. transformer auxiliary winding elimination mosfet transistor series regulator method + + + ic1 in968b 510 k 0.1 w mtp 1n50e figures 31 through 33 show three possible methods of eliminating the transformer auxiliary winding and the associated fast recovery diode and capacitor. these methods are most practical for fixed or narrow range ac line voltage applications. care must be taken when used in wide range ac line voltage applications, as the power dissipation in the voltage dropping elements may become excessive. the shunt regulator method is the most economical but the series pass methods dissipate less power when used in wide range line voltage applications. the mosfet method is the most efficient since the gate requires essentially zero current. the component values shown in the above figures are for a nominal ac line voltage of 115 volts 20%. figure 34. converter softstart ic1 in4148 1.5 k r3 3.6 c5 47 z1 1n757a 9.1 v 15 k 22 k z2 1n752a 5.6 v q2 2n3904 q1 2n3906 47 k 10 k 33 k converter on/off control 0.01 pwm feedback v cc bias source high switch current circuit return from ground pin to negative terminal of capacitor c1. high switch current from transformer t1 to power switch pin. converter softstart can be implemented by separating the connection between pins 1 and 2 with a resistor. initially with the converter in the off state, the internal startup circuit charges capacitor c5 to a voltage that exceeds the vbe of q1 plus the breakdown of z1. this causes transistors q1 and q2 to latch on. since the voltage at pin 2 is now greater than the internal shunt regulator threshold, minimum duty cycle pulses appear at the power switch circuit pin 5. as the voltage across c5 approaches the regulation threshold, the pwm duty cycle will gradually increase until regulation is established at the converter output. upon converter power down, the transistor latch will turn off at approximately 8.0 v which is slightly greater than the devices highest minimum operating voltage specification. this guarantees that softstart will be active upon the next powerup cycle.
mc33369 thru mc33374 22 motorola analog ic device data figure 35. high voltage stepup converter on/off toggle 50 0.01 mc 33374 dc input 100 100 10 + + + + + l boost rectifier dc input z1 z2 3.3 k a simple transformerless high voltage stepup converter can be constructed with any of the devices in this series. the maximum output voltage of this topology is limited by the power switch circuit breakdown of 700 v minus the forward voltage drop of the boost rectifier. the converter requires a minimum input of 15 v to guarantee startup. the regulated output voltage is equal to the sum of the zener voltage drops, plus the shunt regulator threshold, plus the voltage drop across the 3.3 k resistor. the boost rectifier must be a schottky or fast recovery type with sufficient current and voltage capability to meet the converter's output requirements. figure 36. low power offline converter + + mc 33370 + + 50 0.01 1n4006 680* 1n4006 680* 10 92 to 276 vac input *trw flameproof fusable resistor p4ke600 1.0 nf 1n4933 t1 82 100 5.1 v/20 ma dc output mzp 4733a the converter shown above was designed for cost sensitive low power applications that require a line isolated power source. typical applications include consumer and industrial equipment. note that the transformer auxiliary winding has been eliminated and the mc33370 operates continuously in the auto restart mode. this method of converter operation is capable of providing an output power of up to 200 mw.
mc33369 thru mc33374 23 motorola analog ic device data outline dimensions p suffix plastic package case 62605 issue k notes: 1. dimension l to center of lead when formed parallel. 2. package contour optional (round or square corners). 3. dimensioning and tolerancing per ansi y14.5m, 1982. 14 5 8 f note 2 a b t seating plane h j g d k n c l m m a m 0.13 (0.005) b m t dim min max min max inches millimeters a 9.40 10.16 0.370 0.400 b 6.10 6.60 0.240 0.260 c 3.94 4.45 0.155 0.175 d 0.38 0.51 0.015 0.020 f 1.02 1.78 0.040 0.070 g 2.54 bsc 0.100 bsc h 0.76 1.27 0.030 0.050 j 0.20 0.30 0.008 0.012 k 2.92 3.43 0.115 0.135 l 7.62 bsc 0.300 bsc m 10 10 n 0.76 1.01 0.030 0.040 tv suffix plastic package case 314e01 issue o q k f u a b g m 0.010 p m t 5x j m 0.024 t optional chamfer s l w e c h seating plane 5x d v p t n dim min max inches a 0.572 0.613 b 0.390 0.415 c 0.170 0.180 d 0.025 0.038 e 0.048 0.055 f 0.890 0.930 g 0.067 bsc h 0.105 bsc j 0.015 0.025 k 0.900 1.000 l 0.320 0.365 n 0.259 bsc q 0.140 0.153 s 0.620 u 0.468 0.505 v 0.718 w 0.090 0.100 notes: 1. dimensions are in inches. 2. interpret dimensions and tolerances per asme y14.5m, 1994. 3. dimension d does not include dambar protrusion. allowable dambar protrusion shall be 0.005 total in excess of the d dimension at maximum material condition. 12345 t suffix plastic package case 314d04 issue e q 12345 u k d g a b 5 pl j h l e c m q m 0.356 (0.014) t seating plane t dim min max min max millimeters inches a 0.572 0.613 14.529 15.570 b 0.390 0.415 9.906 10.541 c 0.170 0.180 4.318 4.572 d 0.025 0.038 0.635 0.965 e 0.048 0.055 1.219 1.397 g 0.067 bsc 1.702 bsc h 0.087 0.112 2.210 2.845 j 0.015 0.025 0.381 0.635 k 0.990 1.045 25.146 26.543 l 0.320 0.365 8.128 9.271 q 0.140 0.153 3.556 3.886 u 0.105 0.117 2.667 2.972 notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: inch. 3. dimension d does not include interconnect bar (dambar) protrusion. dimension d including protrusion shall not exceed 10.92 (0.043) maximum.
mc33369 thru mc33374 24 motorola analog ic device data sensefet is a trademark of motorola, inc. motorola reserves the right to make changes without further notice to any products herein. motorola makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does motorola assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. atypicalo parameters which may be provided in motorola data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. all operating parameters, including atypicalso must be validated for each customer application by customer's technical experts. motorola does not convey any license under its patent rights nor the rights of others. motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the motorola product could create a situation where personal injury or death may occur. should buyer purchase or use motorola products for any such unintended or unauthorized application, buyer shall indemnify and hold motorola and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that motorola was negligent regarding the design or manufacture of the part. motorola and are registered trademarks of motorola, inc. motorola, inc. is an equal opportunity/affirmative action employer. mfax is a trademark of motorola, inc. how to reach us: usa / europe / locations not listed : motorola literature distribution; japan : nippon motorola ltd.; spd, strategic planning office, 141, p.o. box 5405, denver, colorado 80217. 13036752140 or 18004412447 4321 nishigotanda, shinagawaku, tokyo, japan. 81354878488 customer focus center: 18005216274 mfax ? : rmfax0@email.sps.mot.com touchtone 1 6022446609 asia / pacific : motorola semiconductors h.k. ltd.; 8b tai ping industrial park, motorola fax back system us & canada only 18007741848 51 ting kok road, tai po, n.t., hong kong. 85226629298 http://sps.motorola.com/mfax/ home page : http://motorola.com/sps/ mc33370/d ?

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